1. Field of Invention
The invention relates to processing multiple contexts, and more particularly to a microprocessor using shared pipeline stages to facilitate context switching during processing.
2. Related Art
Electronic processors that execute arithmetic and logical operations (e.g., integrated circuit microprocessors) typically execute a predefined process (a program) in order to complete a particular task. Since such processors are typically assigned many tasks, they execute many corresponding processes to carry out assigned tasks. Pipelining is a well-known method of simultaneously, or nearly simultaneously, executing instructions associated with two or more of such processes. The pipeline moves the data associated with the process through the processor as the processor executes the process. For example, the pipeline may be thought of as the instruction data that moves through the processor as the processor carries out the process. The context under which the processor is operating as it executes a particular pipelined process is the information that is associated with the process being executed by the particular pipeline. During execution of the pipelined process, multiple registers typically store context information associated with the execution. This context information may be, for example, address information, data, a program counter, a stack pointer, and flags (e.g., carry flag). Thus registers store context information that is associated with the pipelined process being executed.
System-on-a-chip (SOC) designs implement an entire electronic system on one integrated circuit chip. SOCs typically include at least one embedded microprocessor and other circuits required to implement the system. Microprocessors that can execute two or more pipelines are known. Typically in such microprocessors, a unique set of registers is associated with each unique pipeline, and each unique register set stores context information that is associated with each unique pipeline. Such registers require on-chip area. As SOC designs become more complex, however, chip area becomes an important design limitation. Therefore, what is required is a way to facilitate the use of multiple pipelines in a microprocessor topology while simultaneously saving chip area.